.....
Example that the Draft 08/26/96 does not solve (B):
Origin 1 Target Origin 2
COMPLETE
WAIT
send to 1
recv
POST
start(MPI_WEAK or STRONG)
put
complete
wait
send to 2
receive
load
post
START(MPI_WEAK or STRONG)
put
... ...
This example does not work with the draft 08/26/96 because
the last start is satisfied by the first post. (Upper case is
used for the sequence matching the rule of MPI_RMA_START in
the draft 08/26/96.) I.e. the last load and put is running
at the same time!
*****
I don't see how the bug could happen. The receive at origin 2 completes after
the wait at Target. Thus, when process 2 executes its start, the target
window is not posted, unless Target process executed its second post. In any
case, the put of process 2 can proceed only after the second post call of the
Target process. In case this is not clear from the text in the current draft,
than the text need be clarified. But, an RMA call following a start can access
a window only when the window is posted. In some cases, the RMA accesses will
be further delayed until a subsequent post occur, but in no case can the access
proceed while the window is not posted.
*******
I also want to remember that this way of synchronization is not good
on virtual shared memory machines like CRAY T3E, because it cannot
be implemented efficiently there.
*****
It would be useful to explain this in more detail. I don't see, off hand,
the relevance.
*******
-
Rolf