Re: relaxed 1-sided model

(no name) (Marc Snir/Watson/IBM Research@nas.nasa.gov)
21 Jun 96 17:52:35

Well, Eric, if you check the design carefully for your system, and so do the
other vendors, then we are in good shape. One cannot prove that the design
works well on all platforms, one can just let this statement stand open for
falsification. Since vendors have a clear inducement not to get saddled with a
standard they find hard to support, I am quite sure that all specific problems
do come out in the open in the process. It seems that both Cray and NEC, that
have semi-shared memory architectures, did look at the details.

Additional weakening of the model cannot impede performance or ease of
implementation, since a valid implementation in the stronger model is still
valid in the weaker model. It can impede useability. Jarek, since you made a
strong argument that such is the case, it would be nice if you would bring in a
concrete example where it matters that updates done by process A to the memory
of process B be available to process C as soon as the put is complete. In any
case, I am quite happy with the current definition, and can live with a weaker
coherence model, if it simplifies implementation in important cases. I am less
sure that I want a directive where the user promises that weak coherence will
suffice. First, such directives provide more rope to the user to hang
himself/herself, by providing the wrong directive. Second, users will have the
expectation that implementations take advantage of such directive, which will
require two different implementation mechanisms.